1. Field of the Invention
The present invention relates to a solid-state imaging device, a method of driving the solid-state imaging device, and a camera.
2. Description of the Related Art
Methods of arranging a plurality of A/D converting units in a MOS-type solid-state imaging device, which includes a plurality of photoelectric conversion elements arranged to be staggered and the plurality of A/D converting units, have been disclosed (see, for example, JP-A-2001-223350).
A MOS-type solid-state imaging device according to a first example of the related art will be described with reference to a block diagram of FIG. 10.
As shown in FIG. 10, in a MOS-type solid-state imaging device 100, a plurality of photoelectric conversion elements 110 each composed of a photodiode are disposed on one surface of a semiconductor substrate 101 such that each photoelectric conversion element deviates from adjacent photoelectric conversion elements in a row direction or a column direction, that is, the photoelectric conversion elements are arranged to be staggered. A plurality of output signal lines 130 are disposed to correspond one-to-one with the photoelectric conversion element columns 111. Each of the output signal lines 130 extends on the left side of the corresponding photoelectric conversion element column 111 along the corresponding photoelectric conversion element column 111 as shown in FIG. 10. Each output signal line 130 is electrically connected to the photoelectric conversion elements 110 in the corresponding photoelectric conversion element column 111 through switching circuit units. An output transistor included in each switching circuit unit can generate an electric detection signal according to the amount of signal charge stored in a corresponding photoelectric conversion element 110 on a corresponding output signal line 130.
A plurality of A/D converting units 140 each are provided on the semiconductor substrate 101 for every two output signal lines 130. Each of the A/D converting units 140 is electrically connected to two corresponding output signal lines 130. Also, each of the A/D converting units 140 is configured to have an A/D converter 145. For example, a plurality of sampling/holding circuit units 141 each are disposed between each A/D converter 145 and two output signal lines 130 corresponding to the A/D converter 145. Each of the A/D converters 145 sequentially generates and outputs digital signals corresponding to the electric detection signals generated on the two corresponding signal lines 130. Since the plurality of photoelectric conversion elements 110 are arranged to be staggered, the electric detection signal is not simultaneously generated on two output signal lines 130 corresponding to one A/D converting unit 140. The electric detection signal is generated on only one of the two output signal lines 130 corresponding to one A/D converting unit 140.
FIG. 11 is a block diagram for explaining a second example of the related art.
As shown in FIG. 11, the basic configuration and operation of a MOS-type solid-state imaging device 200 according to the second example of the related art are the same as those in the first example of the related art. However, in the second example, a plurality of output signal lines 130 each are disposed to meander through corresponding photoelectric conversion element columns 110 in plan view. Therefore, it is possible to reduce the number of output signal lines 130 to half that in the first example.
In the MOS-type solid-state imaging device according to any one of the first and second examples of the related art, a plurality of photoelectric conversion elements 110 are disposed to be staggered. When the above-mentioned configuration is taken, that is, when the plurality of photoelectric conversion elements 110 are arranged to be staggered, one photoelectric conversion element row includes either the photoelectric conversion elements 110 in the even-numbered columns or the photoelectric conversion elements 110 in the odd-numbered columns. Therefore, by providing one A/D converting unit 140 for every two photoelectric conversion element columns 111, each A/D converting unit can separately receive electric signals generated by corresponding output transistors and generate digital signals corresponding to the received electric signals. In this case, as described concerning the first and second examples, it is possible to reduce the total number of A/D converting units 140 to half the total number of photoelectric conversion elements 111. That is, it is possible to reduce the total number of A/D converting units 140 by half in the related art. As a result, even when the integration degree of the photoelectric conversion elements is made high, it is possible to form the A/D converting units 140 without using a highly sophisticated micro-fabrication technique. Accordingly, it is possible to reduce the manufacturing cost.
However, in the examples, the total number of A/D converting units 140 has been made to half the total number of photoelectric conversion element columns 111. Therefore, in the first example, since the column signal lines 130 are connected two-by-two to each A/D converting unit 140, the total length of the column signal lines 130 connected to one A/D converting unit 140 becomes two times larger than that in the related art. In the second example, since the column signal lines 130 each meander through two photoelectric conversion element columns, the length of the column signal line 130 connected to one A/D converting unit 140 becomes two times larger than that in the related art, or the number of photoelectric conversion elements 110 on one column signal line 130 becomes two times larger than that in the related art. As a result, the time it takes to read signals of the photoelectric conversion elements 110 to the column signal lines 130 becomes longer due to the load capacity of the wiring lines or the elements.
In particular, in a CMOS image sensor, generally, an amplifier is provided in a pixel. The amplifier performs amplifying and reading. An amplifying unit of the amplifier performs source-follower reading. In a source-drain reading mode, since amplifying is performed by disposing a current source upside or downside of a column signal line and applying a current to an amplifying transistor of a pixel, when the load capacitor of the amplifying transistor increases, the read time becomes longer.